Created by Eric Zhang(hz9xa)
04/29/2014

****To use these source files, copy them into "source" directory

*This folder contains the source files of FPU in OR1200. 
*Modified verilog files include:
	mul.v 
	div.v
	or1200_fpu_mul.v
	or1200_fpu_div.v
	or1200_fpu_arith.v

*Black box files for top-level synthesis:
	mul.v.bb 
	div.v.bb 
*To use black box synthesis, rename(copy) mul.v.bb to mul.v, 
same for div.v.bb

*Testbench file for VCS:
	fpu_TB_single.v

*other files required by VCS:
	sourcefile.txt  : a list of source files for simulation 
	DW02_mul.v      : contains definition for designware ip DW02_mult
	DW_div.v 	: contains definition for designware ip DW_div

*To run VCS:
	vcs -F sourcefile.txt -R -gui
